1. Field of the Invention
The present invention relates to an output buffer circuit capable of enhancing stability, and more particularly to an output buffer circuit that increases a phase margin of an operational amplifier by adjusting output path impedance of the operational amplifier.
2. Description of the Prior Art
Output buffers are usually applied to various electronic devices for isolating signals from input terminals to output terminals to avoid the input terminals being affected by loading and for enhancing driving ability. In Liquid Crystal Display (LCD) devices, for example, source drivers charge each pixel in LCD panels to an individual voltage level to drive liquid crystal molecules of each pixel by using the output buffers. Hence, the driving ability of the output buffer is highly related to display performance and responding time of the LCD devices.
Please refer to FIG. 1, which is a schematic diagram of a conventional source driver 10. The source driver 10 includes a shift register 11, a data latch (or known as a line buffer) 12, a digital-to-analog converter (DAC) 13, an output buffer 14, and an output switch 15. The shift register 11 is utilized for sequentially receiving image data DATA according to a clock signal CLK. When the image data corresponding to a horizontal scan line data is received, the data latch 12 grabs the data temporarily stored in the shift register 11 according to a data loading signal LOAD generated by a timing controller (not shown), such that the shift register 11 can proceed to receive the image data of a next horizontal scan line. The DAC 13 then converts the digital pixel data stored in the data latch 12 to analog voltages and outputs the analog voltages to the output buffer 14. The output buffer 14 is utilized for providing sufficient driving ability, and the output switch 15 is utilized for sequentially coupling the output buffer 14 to a corresponding data line DL. Accordingly, the data line DL can be drove.
In FIG. 1, the output buffer 14 and the output switch 15 is known as an output buffer circuit of the source driver 10. More specifically, as shown in FIG. 2, the output buffer 14 includes an operational amplifier 110, and the output switch 15 includes a switch SW for forming a signal path to the data line DL via an output pad P of the source driver 10. The operational amplifier 110 has a positive input terminal IN+, a negative input terminal IN− and an output terminal OUT. The positive input terminal IN+ is utilized for receiving an analog voltage. The output terminal OUTPUT is coupled to the negative input terminal IN− to form a negative feedback loop. The operational amplifier 110 is utilized for driving the voltage of the output pad P to a certain voltage level according to the analog voltage received by the positive input terminal IN+. However, in order to drive different pixels of the data line DL at different time, the source driver 10 must renew the analog voltage frequently. The source driver 10 turns off the switch SW when renewing the analog voltage, and turns on the switch SW for outputting the analog voltage being renewed to the data line DL until the data line DL is ready to be charged.
When the switch SW is turned on, the output terminal OUT of the operational amplifier 110 is electrically connected to the data line DL through the output pad P. In general, the stabilization time of the output voltage is determined by capacitive load CLOAD of the date line DL, turn-on impedance of the switch SW and output impedance of the operational amplifier 110. However, in order to decrease power loss, the conventional source driver continuously reduces the DC currents of the output buffer, causing that a phase margin of the operational amplifier is decreased and thus the stabilization time is increased. Under this condition, it is inevitable to postpone the testing time of the output voltage, resulting in the increase of the testing cost.